1. Technical Field
The present invention relates to transmitting packets between a packet controller and network processor. More particularly, the present invention relates to transmitting and receiving packets, capable of improving performance, and reducing a burden of copying the whole packet, by informing the network processor of packet information (a packet address, size, input port, etc.) received from the packet controller and by processing the packet information.
2. Related Art
Due to an explosive increase in the amount of Internet traffic, demands for a variety of services such as MPLS (MultiProtocol Label Switching), MPLS VPN (Virtual Private Network), IP (Internet Protocol) VPN, and QoS (Quality of Service) are increasing as well as a demand for high bandwidth and high speed packet processing.
But, it is difficult to meet time-to-market conditions when using a host processor or ASIC (Application Specific Integrated Circuit) of a related art.
Therefore, a network processor has emerged and present products for high speed packet processing (1G/2.5G/10G) are now being brought into the market, these products having a strong point of programmability for accepting various services, thereby meeting market demand.
An external interface of such a network processor interfaces a switch fabric for its upstream operations and is connected to a data link layer for its downstream operations. The data link layer (layer 2) is delivered to a network processor through a packet controller for mainly processing the relevant data link protocol packet.
Generally, the packet controller handles a packet of the “layer 2”, and the network processor could handle a packet of the “layer 2” through a “layer 7”. In a communication system, packet processing between a packet controller and a network processor frequently occurs and also transmission and reception of a packet between different data link layers occurs. For such processes, a packet conversion process is required.
More particularly, in a communication system for supporting multi-services (e.g. ATM: (Asynchronous Transfer Mode), Ethernet, POS: Packet Over SONET, etc.), such packet conversion is indispensable.
FIG. 1 is a block diagram of an apparatus for transmitting and receiving a packet between a packet controller and a network processor according to a related art. Referring to FIG. 1, an apparatus for transmitting and receiving a packet of a related art includes: a packet controller 11; a first packet buffer 12; a network processor 13; and a second packet buffer 14. The network processor 13 consists of a control packet processing unit 131 and a data packet processing unit 132.
The operation of such an apparatus for transmitting and receiving a packet is as follows. A packet of the “layer 2” is input to the packet controller 11. The input packet is stored in the first packet buffer 12 which belongs to the region of the packet controller 11.
After that, to transmit the packet to the network processor 13, the packet controller 11 copies the input packet stored in the first packet buffer 12 to the second packet buffer 14, delivering an interrupt signal to the control packet processing unit 131 of the network processor 13. The input packet that has been copied to the second packet buffer 14, is packet-converted by the data packet processing unit 132 of the network processor 13 and output.
During a packet processing between the network processor 13 and the packet controller 11, each apparatus processes a packet by copying a packet to its memory region (i.e. the first packet buffer and the second packet buffer, respectively) managed by itself, so that deteriorated performance occurs.
Also, upon transmission and reception of a packet between different data link layers (e.g. ATM→Ethernet), increased process overhead due to packet header differences occur.
U.S. Pat. No. 6,526,053 to Ishiba et al., entitled METHOD AND APPARATUS FOR TRANSMITTING PACKETS AND NETWORK USING THE SAME, issued on Feb. 25, 2003, relates to a packet transmitting method of processing a packet having a control information area and a user information area by a functional block in a node and, thereafter, transmitting the packet from the node. Whether information of the user information area is useless for the user or not is discriminated on the basis of information of the control information area or the user information area. The packet judged to be useless is converted into a predetermined format in which the number of alternating times of a bit pattern has been reduced and the packet is allowed to pass through the functional block. The bit pattern of the packet is returned to a state before the conversion at least before the packet is transmitted from the node.
U.S. Pat. No. 6,434,115 to Schwartz et al., entitled SYSTEM AND METHOD FOR SWITCHING PACKETS IN A NETWORK, issued on Aug. 13, 2002, relates to a switching node for transferring packets, each including a destination address, in a network includes a plurality of input port modules, a plurality of output port modules and a switching fabric, including a packet meta-data processor and a packet switch. Each input port module is connected to a communication link for receiving packets thereover, and each output port module is connected to a communication link for transmitting packets thereover. Each input port module, upon receiving a packet, buffers the packet and generates a meta-data packet therefor identifying the output port module that is to transmit the packet and packet identifier information, and provides it to the packet meta-data processor. The packet meta-data processor receives the meta-data packets generated by all of the input port modules and operational status information from all of the output port modules and for each output port module, processes the meta-data packets received from all of the input port modules in connection with the operational status information to determine whether the packet should be passed or dropped. If the packet meta-data processor determines that a packet associated with a meta-data packet is to be dropped, it will notify the input port module in which the packet is buffered, which, in turn, will discard the packet. On the other hand if the packet meta-data processor determines that the packet associated with the meta-data packet is not to be dropped, it will enqueue the meta-data packet for the associated output port module. Each output port module retrieves meta-data packets from its respective meta-data packet queue maintained therefor by the packet meta-data processor. For each meta-data packet retrieved by an output port module, the output port module will request that the input port module identified in the meta-data packet transfer the packet identified in the input port module thereto through the packet switch. When the output port module receives the packet, it will transmit it over the communication link connected thereto.
U.S. Pat. No. 4,488,289 to Turner, entitled INTERFACE FACILITY FOR A PACKET SWITCHING SYSTEM, issued on Dec. 11, 1984, relates to a communication method and packet switching system in which packets comprising logical addresses and voice/data information are communicated through the system by packet switching networks which are interconnected by high-speed digital trunks with each of the latter being directly terminated on both ends by trunk controllers. During initial call setup of a particular call, central processors associated with each network in the desired route store the necessary logical to physical address information in the controllers which perform all logical to physical address translations on packets of the call. Each network comprises stages of switching nodes which are responsive to the physical address associated with a packet by a controller to communicate this packet to a designated subsequent node. The nodes provide for variable packet buffering, packet address rotation techniques, and intranode and internode signaling protocols. Each packet has a field which is automatically updated by the controllers for accumulating the total time delay incurred by the packet in progressing through the networks. Each processor has the capability of doing fault detection and isolation on the associated network, trunks, and controllers by the transmission of a single test packet. The testing is done solely in response to the test packet and no preconditioning of controllers or networks is necessary.
U.S. Patent Publication No. 2002/0186695 to Schwartz et al., entitled PACKET FORWARDING APPARATUS AND METHOD USING PIPELINED NODE ADDRESS PROCESSING, issued on Dec. 12, 2002, relates to a switching node for transferring packets, each including a destination address, in a network includes a plurality of input port modules, a plurality of output port modules and a switching fabric, including a packet meta-data processor and a packet switch. Each input port module is connected to a communication link for receiving packets thereover, and each output port module is connected to a communication link for transmitting packets thereover. Each input port module, upon receiving a packet, buffers the packet and generates a meta-data packet therefor identifying the output port module that is to transmit the packet and packet identifier information, and provides it to the packet meta-data processor. The packet meta-data processor receives the meta-data packets generated by all of the input port modules and operational status information from all of the output port modules and for each output port module, processes the meta-data packets received from all of the input port modules in connection with the operational status information to determine whether the packet should be passed or dropped. If the packet meta-data processor determines that a packet associated with a meta-data packet is to be dropped, it will notify the input port module in which the packet is buffered, which, in turn, will discard the packet. On the other hand if the packet meta-data processor determines that the packet associated with the meta-data packet is not to be dropped, it will enqueue the meta-data packet for the associated output port module. Each output port module retrieves meta-data packets from its respective meta-data packet queue maintained therefor by the packet meta-data processor. For each meta-data packet retrieved by an output port module, the output port module will request that the input port module identified in the meta-data packet transfer the packet identified in the input port module thereto through the packet switch. When the output port module receives the packet, it will transmit it over the communication link connected thereto.
U.S. Patent Publication No. 2003/0072318 to Lam et al., entitled SYSTEM AND METHOD FOR PACKET FORWARDING, issued on Apr. 17, 2003, relates to a system and method for packet forwarding. The packet forwarding improves the performance of common network security applications. The system includes an operating system kernel, a plurality of packet forwarding paths, and a packet classifier. The method includes means for receiving network packets, means for receiving state information from a plurality of external agents, means for selecting a forwarding path from a plurality of forwarding paths based on the state information, and means for transmitting packets.
U.S. Patent Publication No. 2003/0231631 to Pullela, entitled METHOD AND APPARATUS FOR PROCESSING PACKETS BASED ON INFORMATION EXTRACTED FROM THE PACKETS AND CONTEXT INDICATIONS SUCH AS BUT NOT LIMITED TO INPUT INTERFACE CHARACTERISTICS issued on Dec. 18, 2003, relates to a context vector, typically used in a lookup operation of an associative memory, which is generated based on a context of a received packet and the packet itself. In one implementation, multiple interfaces can share a common access control list as the context vector provides an indication of the result of unique processing required because of varying contexts, such as, but not limited to different interfaces, source addresses, and virtual network addresses. One implementation includes an input interface circuitry, a context indicator generator, a lookup word field generator, and an associative memory. The context indicator generator generates a context vector corresponding to a characteristic of the input interface circuitry. The lookup word field generator generates one or more lookup word vectors based on the packet. The associative memory performs a lookup operation based on the context vector and lookup word vectors.
U.S. Patent Publication No. 2003/0110229 to Kulig et al, entitled SYSTEM AND METHOD FOR CONTROLLING TRANSMISSION OF DATA PACKETS OVER AN INFORMATION NETWORK, issued on Jun. 12, 2003, relates to an apparatus for controlling transmission of data packets in an information network which comprises a Regional Transaction Processor (RTP) operable to communicate with a Data Enabling Device (DED) and at least one workstation. The DED searches data packets for content match information. The RTP includes instructions to generate information to include in a prompt to be presented at the workstation when the content match information is detected in at least one of the data packets. The prompt is based on information in the data packet. Transmission of the data packets through the information network is suspended by the DED until a response to the prompt is received that authorizes downloading the data packets to the workstation. If transmission of the data packets to the workstation is not authorized, the data packets are discarded by the DED.
While each of the afore-cited references have features in common with the present invention, none of these references teach or suggest the present invention, namely, an apparatus and method for transmitting and receiving a packet, capable of improving performance, and reducing a burden of copying the whole packet, by informing the network processor of packet information (a packet address, size, input port, etc.) received from the packet controller, and by processing the information.